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A.10 Exception flags signals

DEFLAGS and SCUEVABORT signals are the Exception flag signals.

Table A-24 Exception flags signals

Name I/O Destination Description
DEFLAGSn[6:0] O System integrity controller

Data Engine output flags. Only implemented if the Cortex®‑A9 processor includes a Data Engine.

If the DE is NEON SIMD unit:

  • Bit[6] gives the value of FPSCR[27]
  • Bit[5] gives the value of FPSCR[7]
  • Bits[4:0] give the value of FPSCR[4;0].

If the DE is FPU:

  • Bit[6] is zero.
  • Bit[5] gives the value of FPSCR[7]
  • Bits[4:0] give the value of FPSCR[4;0].
SCUEVABORT O Indicates an external abort has occurred during a coherency writeback. SCUEVABORT is a pulse signal that is asserted for one CLK clock cycle.

For additional information on the FPSCR, see the ARM® Cortex®‑A9 Floating-Point Unit (FPU) Technical Reference Manual and the ARM® Cortex®‑A9 NEON™ Media Processing Engine Technical Reference Manual.

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