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A.15 PTM interface signals

List of PTM interface signals. There can be as many PTM interface signal buses as there are Cortex®‑A9 processors in the design.

Table A-34 PTM interface signals

Name I/O

Source or

destination

Description

WPTFIFOEMPTYn

O PTM device There are no speculative waypoints in the PTM interface FIFO.
WPTCOMMITn[1:0] O

Number of waypoints committed this cycle. It is valid to indicate a valid waypoint and commit it in the same cycle.

WPTCONTEXTIDn[31:0] O

Context ID for the waypoint.

This signal must be true regardless of the condition code of the waypoint.

WPTENABLEn I Enable waypoint. When set, enables the Cortex‑A9 processor to output waypoints.
WPTEXCEPTIONTYPEn[3:0] O

Exception type:

0b0001Halting Debug.
0b0010Secure Monitor.
0b0100Imprecise Data Abort.
0b0101T2EE trap.
0b1000Reset.
0b1001UNDEF.
0b1010SVC.
0b1011Prefetch abort/Software Breakpoint.
0b1100Precise data abort/software watchpoint.
0b1110IRQ.
0b1111FIQ.
WPTFLUSHn O

Flush signal from core exception FIFO. All as yet uncommitted waypoints are flushed.

WPTLINKn O

The waypoint is a branch and updates the link register.

Only HIGH if WPTTYPE[2:0] is a direct branch or an indirect branch.

WPTnSECUREn O PTM device

Instructions following the waypoint are executed in Non-secure state. An instruction is in Non-secure state if the NS bit is set and the processor is not in secure monitor mode.

WPTPCn [31:0] O

Waypoint last executed address indicator.

This is the base LR in the case of an exception.

Must be 0 for a reset exception, when it must not be traced.Equal to 0 if the waypoint is reset exception.

WPTT32LINKn O

Indicates the size of the last executed address when in Thumb state:

016-bit instruction.
132-bit instruction.
WPTTAKENn O

The waypoint passed its condition codes. The address is still used, irrespective of the value of this signal.

Must be set for all waypoints except branch.

WPTTARGETJBITn O

J bit for waypoint destination.

This signal is LOW if WPTTRACEPROHIBITED is asserted.

WPTTARGETPCn[31:0] O

Waypoint target address:

  • Bit [1] must be zero if T-bit is zero.
  • Bit [0] must be zero if J-bit is zero.

The value is zero if WPTTYPE is either prohibit or debug.

WPTTARGETTBITn O

T bit for waypoint destination

This signal is LOW if WPTTRACEPROHIBITED is asserted.

WPTTRACEPROHIBITEDn O PTM device

Trace is prohibited for the waypoint target.

Indicates entry to prohibited region. No more waypoints are traced until trace can resume.

Indication that PTM clocks can be stopped.

This signal must be permanently asserted if NIDEN and DBGEN are both LOW, after the in-flight waypoints have exited the core. Either an exception or a serial branch is required to ensure that changes to the inputs have been sampled.

Only one WPTVALID cycle can be seen with WPTTRACEPROHIBITED set.

Trace stops with this waypoint and the next waypoint seen is an Isync packet.

WPTTYPEn[2:0] O

Waypoint Type.

0b000Direct Branch.
0b001Indirect Branch.
0b010Exception.
0b011DMB.
0b100Debug entry/Trace prohibited.
0b101Debug exit, requires addresses of first instruction.
0b110Invalid.
0b111Invalid.

Must only take valid states when WPTVALID is HIGH.

Debug Entry must be followed by Debug Exit.

Note

Debug exit does not reflect the execution of an instruction.
WPTVALIDn O

Waypoint is confirmed as valid.

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