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A.3 Interrupts

List of interrupt line signals.

Table A-5 Interrupt line signals

Name I/O

Source

Description
IRQS[x:0] I Interrupt sources

Interrupt distributor interrupt lines.

x can be 31, 63,…, up to 223 by increments of 32. If there are no interrupt lines this pin is removed.

See Chapter 3 Interrupt Controller.

nIRQ[N:0] I

Individual Cortex®‑A9 processor legacy IRQ request input lines.

Active-LOW interrupt request:

0Activate interrupt.
1Do not activate interrupt.

The processor treats the nIRQ input as level sensitive. To guarantee that an interrupt is taken, ensure the nIRQ input remains asserted until the processor acknowledges the interrupt.

nFIQ[N:0] I

Individual Cortex‑A9 processor private FIQ request input lines.

Active-LOW fast interrupt request:

0Activate fast interrupt.
1Do not activate fast interrupt.

The processor treats the nFIQ input as level sensitive. To guarantee that an interrupt is taken, ensure the nFIQ input remains asserted until the processor acknowledges the interrupt.

nIRQOUT[N:0] O Power controller

Active-LOW output of individual processor nIRQ from the Interrupt Controller. For use when processors are powered off and interrupts are handled by the Interrupt Controller under the control of an external power controller.

nFIQOUT[N:0] O

Active-LOW output of individual processor nFIQ from the Interrupt Controller. For use when processors are powered off and interrupts are handled by the Interrupt Controller under the control of an external power controller.

Note

For IRQS[x:0], nIRQ[N:0], and nFIQ[N:0], the minimum pulse width of signals driving external interrupt lines is one PERIPHCLK cycle.
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