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A.4 Configuration signals

List of configuration signals.

Table A-6 Configuration signals

Name I/O

Source or

destination

Description
CFGEND[N:0] I System configuration

Individual Cortex®‑A9 processor endianness configuration.

Forces the EE bit in the CP15 c1 Control Register (SCTLR) to 1 at reset so that the Cortex‑A9 processor boots with big-endian data handling.

0EE bit is LOW.
1EE bit is HIGH.

This pin is only sampled during reset of the processor.

CFGNMFI[N:0] I

Individual Cortex‑A9 processor configuration of fast interrupts to be non-maskable:

0Clear the NMFI bit in the CP15 c1 Control Register.
1Set the NMFI bit in the CP15 c1 Control Register.

This pin is only sampled during reset of the processor.

CLUSTERID[3:0] I

Value read in Cluster ID register field, bits[11:8] of the MPIDR.

FILTEREN I

For use with configurations with two master ports. Enables filtering of address ranges at reset. See  SCU Control Register for information on setting this signal.

FILTERSTART[31:20] I For use with configurations with two master ports. Specifies the start address for address filtering at reset. See  Filtering Start Address Register.
FILTEREND[31:20] I For use with configurations with two master ports. Specifies the end address for address filtering. See  Filtering End Address Register.
PERIPHBASE[31:13] I

Specifies the base address for Timers, Watchdogs, Interrupt Controller, and SCU registers. Only accessible with memory-mapped accesses. This value can be retrieved by a Cortex‑A9 processor using the CP15 c15 Configuration Base Address Register.

SMPnAMP[N:0] O System integrity controller

Signals AMP or SMP mode for each Cortex‑A9 processor.

0Asymmetric.
1Symmetric.
TEINIT[N:0] I System configuration

Individual Cortex‑A9 processor out-of-reset default exception handling state. When set to:

0ARM.
1Thumb.

This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.TE.

VINITHI[N:0] I

Individual Cortex‑A9 processor control of the location of the exception vectors at reset:

0Exception vectors start at address 0x00000000.
1Exception vectors start at address 0xFFFF0000.

This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.V.

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