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A.7 Power management signals

List of power control interface signals.

Table A-9 Power control interface signals

Name I/O

Source or

Destination

Description

CPUCLAMP[N:0]

I Power controller

Interrupt interface clamps control signals:

CPUCLAMP[3]
CPU3 interface.
CPUCLAMP[2]
CPU2 interface.
CPUCLAMP[1]
CPU1 interface.
CPUCLAMP[0]
CPU0 interface.

CPURAMCLAMP[N:0]

I

Enables the clamp cells in Dormant mode.

SCURAMCLAMP

I

Enables the SCU clamp cells in Dormant mode.

NEONCLAMP[N:0]

a
I

Activates the Cortex®â€‘A9 MPE SIMD logic clamps:

0Clamps not active.
1Clamps active.
PWRCTLI0[1:0] I

Reset value for CPU0 status field, bits [1:0] of SCU CPU Power Status Register.

PWRCTLI1[1:0] I

Reset value for CPU1 status field, bits [9:8] of SCU CPU Power Status Register.

PWRCTLI2[1:0] I

Reset value for CPU2 status field, bits [17:16] of SCU CPU Power Status Register.

PWRCTLI3[1:0] I

Reset value for CPU3 status field, bits [25:24] of SCU CPU Power Status Register.

PWRCTLO0[1:0] O
0b0xCPU0 must be powered on.
0b10CPU0 can enter dormant mode.
0b11CPU0 can enter powered-off mode.
PWRCTLO1[1:0] O
0b0xCPU1 must be powered on.
0b10CPU1 can enter dormant mode.
0b11CPU1 can enter powered-off mode.

This signal exists only if CPU1 is present.

PWRCTLO2[1:0] O Power controller
0b0xCPU2 must be powered on.
0b10CPU2 can enter dormant mode.
0b11CPU2 can enter powered-off mode.

This signal exists only if CPU2 is present.

PWRCTLO3[1:0] O
0b0xCPU3 must be powered on.
0b10CPU3 can enter dormant mode.
0b11CPU3 can enter powered-off mode.

This signal exists only if CPU3 is present.

SCUIDLE O L2C-310 or power controller

In the case of the L2C-310, the SCUIDLE output of the Cortex‑A9 MPCore can be connected to the STOPCLK input of the L2C-310.

a

Only if an MPE is present.

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