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Individual Cortex-A9 processor power management

Description of power modes in the processor.

About power modes

There are four power management modes available. These modes are run, standby, dormant, and shutdown.

Place holders for clamps are inserted around each Cortex®â€‘A9 processor so that implementation of different power domains can be eased. It is the responsibility of software to signal to the Snoop Control Unit and the Distributed Interrupt Controller that a Cortex‑A9 processor is shut off so that the Cortex‑A9 processor can be seen as non-existent in the cluster. Each Cortex‑A9 processor can be in one of the following modes:

Run mode
Everything is clocked and powered-up
Standby mode
The CPU clock is stopped. Only logic required for wake-up is still active.
Dormant mode
Everything is powered off except RAM arrays that are in retention mode.
Shutdown
Everything is powered-off.

The following table shows the individual power modes.

Table 5-2 Cortex‑A9 MPCore power modes

Mode Cortex‑A9 processor logic RAM arrays Wake-up mechanism
Run Mode

Powered-up

Everything clocked

Powered-up N/A
Standby modes

Powered-up

Only wake-up logic clocked

Powered-up

Standard Standby modes wake up events. See Standby modes.

Dormant Powered-off Retention state/voltage External wake-up event to power controller, that can perform a reset of the processor.
Shutdown Powered-off Powered-off External wake-up event to power controller, that can perform a reset of the processor.

Entry to Dormant or powered-off mode must be controlled through an external power controller. The CPU Status Register in the SCU is used with the CPU WFI entry flag to signal to the power controller the power domain that it can cut, using the PWRCTL bus.

Run mode

Run mode is the normal mode of operation, where all the functionality of the Cortex®â€‘A9 processor is available.

Standby modes

WFI and WFE Standby modes disable most of the clocks in a processor, while keeping its logic powered up. This reduces the power drawn to the static leakage current, leaving a tiny clock power overhead requirement to enable the device to wake up.

Entry into WFI Standby mode is performed by executing the WFI instruction.

The transition from the WFI Standby mode to the Run mode is caused by:

  • An IRQ interrupt, regardless of the value of the CSPR.I bit.
  • An FIQ interrupt, regardless of the value of the CSPR.F bit.
  • An asynchronous abort, regardless of the value of the CPSR.A bit.
  • A debug event, if invasive debug is enabled and the debug event is permitted.
  • A CP15 maintenance request broadcast by other processors.

Entry into WFE Standby mode is performed by executing the WFE instruction.

The transition from the WFE Standby mode to the Run mode is caused by:

  • An IRQ interrupt, unless masked by the CPSR.I bit.
  • An FIQ interrupt, unless masked by the CPSR.F bit.
  • An asynchronous abort, unless masked by the CPSR.A bit.
  • A debug event, if invasive debug is enabled and the debug event is permitted.
  • The assertion of the EVENTI input signal.
  • The execution of an SEV instruction on any processor in the multiprocessor system.
  • A CP15 maintenance request broadcast by other processors.

The debug request can be generated by an externally generated debug request, using the EDBGRQ pin on the Cortex‑A9 processor, or from a Debug Halt instruction issued to the Cortex‑A9 processor through the APB debug port.

The debug channel remains active throughout a WFI instruction.

Note

When a processor in Standby mode receives an SCU coherency request, the clock on its L1 memory system is restored temporarily so that the request can be handled. This mechanism prevents the requirement for a processor about to enter Standby mode from having to flush its L1 data cache by ensuring that its coherent data remain accessible by other processors.

Dormant mode

Dormant mode is designed to enable the Cortex®â€‘A9 processor to be powered down, while leaving the caches powered up and maintaining their state.

The RAM blocks that are to remain powered up must be implemented on a separate power domain, and there is a requirement to clamp all the inputs to the RAMs to a known logic level, with the chip enable being held inactive. This clamping is not implemented in gates as part of the default synthesis flow because it would contribute to a tight critical path. Implementations that want to implement Dormant mode must add these clamps around the RAMs, either as explicit gates in the RAM power domain, or as pull-down transistors that clamp the values while the Cortex‑A9 processor is powered down. The RAM blocks that must remain powered up during Dormant mode are:

  • All Data RAMs associated with the cache.
  • All Tag RAMs associated with the cache.

Before entering Dormant mode, the state of the Cortex‑A9 processor, excluding the contents of the RAMs that remain powered up in dormant mode, must be saved to external memory. These state saving operations must ensure that the following occur:

  • All ARM registers, including CPSR and SPSR registers are saved.
  • All system registers are saved.
  • All debug-related state must be saved.
  • The Cortex‑A9 processor must correctly set the CPU Status Register in the SCU so that it enters Dormant Mode.
  • A Data Synchronization Barrier instruction is executed to ensure that all state saving has been completed.
  • The Cortex‑A9 processor then communicates with the power controller that it is ready to enter dormant mode by performing a WFI instruction so that power control output reflects the value of SCU CPU Status Register.

Transition from Dormant mode to Run mode is triggered by the external power controller. The external power controller must assert reset to the Cortex‑A9 processor until the power is restored. After power is restored, the Cortex‑A9 processor leaves reset, and by interrogating the power control register in SCU, can determine that the saved state must be restored.

Shutdown mode

Shutdown mode has the entire device powered down, and all state, including cache, must be saved externally by software.

The part is returned to the run state by the assertion of reset. This state saving is performed with interrupts disabled, and finishes with a DSB operation. The Cortex‑A9 processor then communicates with a power controller that the device is ready to be powered down in the same manner as when entering Dormant Mode.

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