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Interrupt Configuration Registers

Summary of the implementation defined features of the ICDICFR.

Each bit-pair describes the interrupt configuration for an interrupt. The options for each pair depend on the interrupt type as follows:

SGIThe bits are read-only and a bit-pair always reads as 0b10.

The bits are read-only

PPI[1] and [4]:0b01

Interrupt is active LOW level sensitive.

PPI[0], [2],and[3]:0b11
Interrupt is rising-edge sensitive.

The LSB bit of a bit-pair is read-only and is always 0b1. You can program the MSB bit of the bit-pair to alter the triggering sensitivity as follows:


Interrupt is active HIGH level sensitive

0b11Interrupt is rising-edge sensitive.

There are 31 LSPIs, interrupts 32-62. You can configure and then lock these interrupts against more change using CFGSDISABLE. The LSPIs are present only if the SPIs are present.

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