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PPI Status Register

Characteristics and bit assignments of the ICPPISR.

Purpose

Enables a Cortex®‑A9 processor to access the status of the inputs on the distributor:

  • PPI(4) is for nIRQ<n>
  • PPI(3) is for watchdog interrupts
  • PPI(2) is for private timer interrupts
  • PPI(1) is for nFIQ<n>
  • PPI(0) is for the global timer.
Usage constraints

A Cortex‑A9 processor can only read the status of its own PPI and therefore cannot read the status of PPI for other Cortex‑A9 processors.

ConfigurationsAvailable in all Cortex‑A9 multiprocessor configurations.
AttributesSee the register summary in  Distributor register summary.

The following figure shows the ICPPISR bit assignments.

Figure 3-5 ICPPISR bit assignments


The following table shows the ICPPISR bit assignments.

Table 3-6 ICPPISR bit assignments

Bits Name Function
[31:16] -

Reserved

[15:11]

ppi_status

Returns the status of the PPI(4:0) inputs on the distributor:

  • PPI[4] is nIRQ
  • PPI[3] is the private watchdog
  • PPI[2] is the private timer
  • PPI[1] is nFIQ
  • PPI[0] is the global timer.

PPI[1] and PPI[4] are active LOW

PPI[0], PPI[2], and PPI[3] are active HIGH.

Note

These bits return the actual status of the PPI(4:0) signals. The ICDISPRn and ICDICPRn registers can also provide the PPI(4:0) status but because you can write to these registers then they might not contain the actual status of the PPI(4:0) signals.
[10:0] - SBZ
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