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SPI Status Registers

Characteristics and bit assignments of the ICSPISRn.

PurposeEnables a Cortex®‑A9 processor to access the status of IRQS[N:0] inputs on the distributor.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all Cortex‑A9 multiprocessor configurations.
AttributesSee the register summary in  Distributor register summary.

The following figure shows the ICSPISRn bit assignments.

Figure 3-6 ICSPISRn bit assignments

The following table shows the ICSPISRn bit assignments.

Table 3-7 ICSPISRn bit assignments

Bits Name Function
[31:0] spi_status

Returns the status of the IRQS[N:0] inputs on the distributor:

Bit [X] = 0IRQS[X] is LOW
Bit [X] = 1IRQS[X] is HIGH.


  • The IRQS that X refers to depends on its bit position and the base address offset of the spi_status Register as the following figure shows.
  • These bits return the actual status of the IRQS signals. The pending_set and pending_clr Registers can also provide the IRQS status but because you can write to these registers then they might not contain the actual status of the IRQS signals.

The following figure shows the address map that the distributor provides for the SPIs.

Figure 3-7 ICSPISRn address map

In this figure, the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding Cortex‑A9 processor interface. The distributor provides up to seven registers. If you configure the Interrupt Controller to use fewer than 224 SPIs, then it reduces the number of registers accordingly. For locations where interrupts are not implemented then the distributor:

  • Ignores writes to the corresponding bits.
  • Returns 0 when it reads from these bits.
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