SPI Status Registers
Characteristics and bit assignments of the ICSPISRn.
|Purpose||Enables a Cortex®‑A9 processor to access the status of IRQS[N:0] inputs on the distributor.|
|Usage constraints||There are no usage constraints.|
|Configurations||Available in all Cortex‑A9 multiprocessor configurations.|
|Attributes||See the register summary in Distributor register summary.|
The following figure shows the ICSPISRn bit assignments.
Figure 3-6 ICSPISRn bit assignments
The following table shows the ICSPISRn bit assignments.
Table 3-7 ICSPISRn bit assignments
Returns the status of the IRQS[N:0] inputs on the distributor:
The following figure shows the address map that the distributor provides for the SPIs.
Figure 3-7 ICSPISRn address map
In this figure, the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding Cortex‑A9 processor interface. The distributor provides up to seven registers. If you configure the Interrupt Controller to use fewer than 224 SPIs, then it reduces the number of registers accordingly. For locations where interrupts are not implemented then the distributor:
- Ignores writes to the corresponding bits.
- Returns 0 when it reads from these bits.