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CPU Interface Implementer Identification Register

Characteristics and bit assignments for the ICCIIDR Register.

PurposeProvides information about the implementer and the revision of the controller.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all Cortex®‑A9 multiprocessor configurations.
AttributesSee the register summary in  Processor interface register summary.

The following figure shows the ICCIIDR bit assignments.

Figure 3-8 ICCIIDR bit assignments


The following table shows the ICCIIDR bit assignments.

Table 3-9 ICCIIDR bit assignments

Bits Values Name Function
[31:20] 0x390 Part number

Identifies the peripheral.

[19:16] 0x1 Architecture version

Identifies the architecture version.

[15:12] 0x2 Revision number

Returns the revision number of the Interrupt Controller. The implementer defines the format of this field.

[11:0] 0x43B Implementer

Returns the JEP106 code of the company that implemented the Cortex‑A9 processor interface RTL. It uses the following construct:

[11:8]The JEP106 continuation code of the implementer.
[7]0.
[6:0]The JEP106 code [6:0] of the implementer.
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