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The Interrupt Controller provides the facility to prevent write accesses to critical configuration registers when you assert CFGSDISABLE. This signal controls write behavior for the secure control registers in the distributor and Cortex®‑A9 processor interfaces, and the Lockable Shared Peripheral Interrupts (LSPIs) in the Interrupt Controller.

If you use CFGSDISABLE, ARM recommends that you assert CFGSDISABLE during the system boot process, after the software has configured the registers. Ideally, the system must only deassert CFGSDISABLE if a hard reset occurs.

When CFGSDISABLE is HIGH, the Interrupt Controller prevents write accesses to the following registers in the:

The Secure enable of the ICDDCR.
Secure interrupts defined by LSPI field in the ICDICTR:
  • Interrupt Security Registers
  • Interrupt Set-Enable Registers
  • Interrupt Clear-Enable Registers
  • Interrupt Set-Pending Registers
  • Interrupt Clear-Pending Registers
  • Interrupt Priority Registers
  • Interrupt Configuration Register.
Cortex‑A9 interrupt interfaces
The ICCICR, except for the EnableNS bit.

After you assert CFGSDISABLE, it changes the register bits to read-only and therefore the behavior of these secure interrupts cannot change, even in the presence of rogue code executing in the secure domain.

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