List of functional clock inputs of the processor and an example of the PERIPHCLK.
The Cortex®‑A9 MPCore processor does not have any asynchronous interfaces. Therefore, all the bus interfaces and the interrupt signals must be synchronous with reference to CLK.
This is the main clock of the Cortex‑A9 processor.
All Cortex‑A9 processors in the Cortex‑A9 MPCore processor and the SCU are clocked with a distributed version of CLK.
The Interrupt Controller, global timer, private timers, and watchdogs are clocked with PERIPHCLK.
PERIPHCLK must be synchronous with CLK, and the PERIPHCLK clock period, N, must be configured as a multiple of the CLK clock period. This multiple N must be equal to, or greater than two.
- This is the clock enable signal for the Interrupt Controller and timers. The PERIPHCLKEN signal is generated at CLK clock speed. PERIPHCLKEN HIGH on a CLK rising edge indicates that there is a corresponding PERIPHCLK rising edge.
The following figure shows an example with the PERIPHCLK clock period N as three.
Figure 5-1 Three-to-one timing ratio