Communication to the Power Management Controller
Communication between the Cortex®â€‘A9 processor and the external Power Management Controller can be performed using the PWRCTLOn Cortexâ€‘A9 MPCore output signals and Cortexâ€‘A9 MPCore input clamp signals.
|PWRCTLOn Cortexâ€‘A9 MPCore output signals||These signals constrain the external Power Management Controller. The value of PWRCTLOn depends on the value of the SCU CPU Status Register. The SCU CPU Status Register value is only copied to PWRCTLOn after the Cortexâ€‘A9 processor signals that it is ready to enter low-power mode by executing a WFI instruction and subsequent STANDBYWFI pin assertion.|
|Cortexâ€‘A9 MPCore input signals||The external Power Management Controller uses CPUCLAMP[3:0], NEONCLAMP[3:0], and CPURAMCLAMP[4:0] to isolate Cortexâ€‘A9 MPCore power domains from one another before they are turned off. These signals are only meaningful if the Cortexâ€‘A9 MPCore processor has been implemented with power clamps designed in.|