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Features

The CoreSight™ SoC-400 provides many features to enable rapid and efficient debugging.

Some of the features provided by CoreSight SoC-400 are:

  • Access to debug features and on-chip AXI, AHB, APB, and JTAG buses through a JTAG or Serial Wire Debug (SWD) interface.
  • Merging of multiple trace sources into a single trace stream.
  • Configurable trace bus widths between 8 bits and 128 bits, with upsizing and downsizing between different widths.
  • Capture of trace streams on-chip or off-chip.
  • Cross-triggering between different debug and trace components.
  • Timestamp generation and system-wide compressed timestamp distribution, including local interpolation to provide local high-resolution timestamps synchronized to a global low-resolution timestamp.
  • Support for inserting synchronous and asynchronous clock domain boundaries and power domain boundaries across internal interfaces.
  • Improved configurability of components to better optimize area and power consumption.
  • Integration with supported ARM® processors.
  • Integration of STM and TMC, licensed separately.
  • IP-XACT views of all components, defining interfaces, signals, configurability, and programmers models.
  • Power intent for all components in Unified Power Format (UPF), including definitions of how signals must be clamped when parts of the system are powered down.
  • Synthesis flow.
  • Flow to verify correct CoreSight system integration.
  • Optional support for AMBA® Designer, enabling graphical component configuration, system stitching, and verification.
  • Full compliance with the CoreSight architecture, enabling integration of third-party IP and comprehensive tools support.
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