APB Interconnect with ROM table
The APB interconnect connects one or more APB bus masters, for example an APB-AP and an APB interface driven by an on-chip processor. APB interconnects can be cascaded, for example to split across multiple clock or power domains.
Each APB Interconnect implements a ROM table at address
which identifies the locations of the CoreSight™ components accessed
The APB Interconnect implements a 32-bit data bus.
This section contains the following subsections: