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DPE-400 enables transportation of bit-per-byte odd parity information plus one parity validity bit for AXI WDATA and RDATA (or AHB-Lite HWDATA and HRDATA) payload.

This information is transported on the WUSER and RUSER (or AHB-Lite HWUSER and HRUSER) bits. The USER signals can be used exclusively for parity information or they can also contain extra user-defined information.

In either case, the parity information resides in the lowest part of the USER signal vector. USER[0] describes the parity validity and USER[(data_width div 8):1] contains the bit per byte parity information.


data_width is a parameter which can be set to 32-bit, 64-bit, 128-bit, or 256-bit.

The data_width must be large enough to accommodate the parity vector for the widest data width in the system. The USER bit reserved for parity information is a consistent width across all interfaces, regardless of the interface data width.

When an interface is the maximum system data width, all the parity bits are used to describe the parity of the data payload irrespective of transfer width.

When an interface is less than the system data width, the lowest indexed bits of the vector are used to describe the parity information of the interface. This is irrespective of transfer width, and the upper bits that are reserved for describing parity information, are ignored on input and driven to '0' on output.

When data width conversion is not present, the parity information and WDATA payload are not impacted by WSTRB.

When data width conversion occurs, WDATA is optimized depending on the value of WSTRB. In this case, data parity is modified to reflect the new WDATA value. A byte of WDATA is driven to 0x00 when the byte-lane’s WSTRB is 1’b0. Therefore, the relevant bit is driven to 1’b1.