You copied the Doc URL to your clipboard.

PMU interrupts

The Neoverse™ N1 core asserts the nPMUIRQ signal when the PMU generates an interrupt.

You can route this signal to an external interrupt controller for prioritization and masking. This is the only mechanism that signals this interrupt to the core.

This interrupt is also driven as a trigger input to the CTI. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information.

Was this page helpful? Yes No