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C5.3 implementation defined features of SPE

This section describes the implementation defined features of SPE.

Events definition

The Neoverse™ N1 core includes a 16-bit event packet which is defined in the following table.

Bit Definition
15 Reserved
14 Reserved
13 Reserved
12 Late prefetch
11 Reserved
10 Remote access
9 Last level cache miss
8 Last level cache access
7 Branch mispredicted
6 Not taken
5 DTLB walk
4 TLB access
3 L1 data cache refill
2 L1 data cache access
1 Architecturally retired
0 Generated exception

Data source packet

The Neoverse N1 core provides an 8-bit data source for load and store operations as defined in the following table. All other values are reserved.

Value Name
0b0000 L1 data cache
0b1000 L2 cache
0b1001 Peer CPU
0b1010 Local cluster
0b1011 System cache
0b1100 Peer cluster
0b1101 Remote
0b1110 DRAM
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