Accessing the feature identification registers
Software can identify the Advanced SIMD and floating-point features using the feature identification registers in the AArch64 Execution state only.
The Cortex®‑A76 core only supports AArch32 in EL0, therefore none of the feature identification registers are accessible in the AArch32 Execution state.
You can access the feature identification registers in the AArch64 Execution
state using the
MRS instruction, for example:
MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt MRS <Xt>, MVFR0_EL1 ; Read MVFR0_EL1 into Xt MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt
Table A10-1 AArch64 Advanced SIMD and scalar floating-point feature identification registers
|MVFR0_EL1||See MVFR0_EL1, Media and VFP Feature Register 0, EL1.|
|MVFR1_EL1||See MVFR1_EL1, Media and VFP Feature Register 1, EL1.|
|MVFR2_EL1||See MVFR2_EL1, Media and VFP Feature Register 2, EL1.|