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Arm Cortex‑A76 Core Technical Reference Manual : Product revisions

Product revisions

This section indicates the first release and, in subsequent releases, describes the differences in functionality between product revisions.

r0p0
First release.
r1p0
Further development and optimization of the product, including updates to the L2 data RAM control inputs to allow multi-cycle hold timing constraints to ease timing closure.
r2p0
Includes Inter-Exception level isolation of branch predictor structures so that an Exception Level cannot train branch prediction for a different Exception Level to reliability hit in these trained prediction entries. Implemented new barrier SSBB.
r3p0
Implemented new barriers PSSBB and CSDB. Support for Speculative Store Bypass Safe (SSBS) bit enabling software to indicate whether hardware is permitted to load or store speculatively.
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