You copied the Doc URL to your clipboard.

Arm Cortex‑A76 Core Technical Reference Manual : Product revisions

Product revisions

This section indicates the first release and, in subsequent releases, describes the differences in functionality between product revisions.

First release.
Further development and optimization of the product, including updates to the L2 data RAM control inputs to allow multi-cycle hold timing constraints to ease timing closure.
Includes Inter-Exception level isolation of branch predictor structures so that an Exception Level cannot train branch prediction for a different Exception Level to reliability hit in these trained prediction entries. Implemented new barrier SSBB.
Implemented new barriers PSSBB and CSDB. Support for Speculative Store Bypass Safe (SSBS) bit enabling software to indicate whether hardware is permitted to load or store speculatively.
Was this page helpful? Yes No