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Arm Cortex‑A76 Core Technical Reference Manual : L1 instruction-side memory system

L1 instruction-side memory system

The L1 instruction memory system has the following key features:

  • Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, Physically Tagged (PIPT) 4-way set-associative L1 data cache.
  • Fixed cache line length of 64 bytes.
  • Pseudo-LRU cache replacement policy.
  • 256-bit read interface from the L2 memory system.
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