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Arm Cortex‑A76 Core Technical Reference Manual : Data cache disabled behavior

Data cache disabled behavior

If the data cache is disabled, load and store instructions do not access any of the L1 data, L2 cache, and, if present, the DSU L3 cache arrays.

Unless the data cache is enabled, a new line is not allocated in the L2 or L3 caches due to an instruction fetch

Data cache maintenance operations are an exception. If the data cache is enabled, the data cache maintenance operations execute normally.

If the data cache is disabled, all loads and store instructions to cacheable memory are treated as if they were non-cacheable. Therefore, they are not coherent with the caches in this core or the caches in other cores, and software must take this into account.

The L2 and L1 data caches cannot be disabled independently.

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