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Arm Cortex‑A76 Core Technical Reference Manual : Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data

Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data

The core data cache consists of a 4-way set-associative structure.

The encoding, which is set in Rd in the appropriate MCR instruction, used to locate the required cache data entry for tag, data, and TLB memory is shown in the following tables. It is similar for both the tag RAM, data RAM, and TLB access. Data RAM access includes an additional field to locate the appropriate doubleword in the cache line.

Tag RAM encoding includes an additional field to select which one of the two cache channels must be used to perform any access.

Table A6-14 L1 data cache tag location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x08
[23:20] Reserved
[19:18] Way
[17]

Copy

0Tag RAM associated with Pipe 0
1Tag RAM associated with Pipe 1
[16:14] Reserved
[13:6] Index [13:6]
[5:0] Reserved

Table A6-15 L1 data cache data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x09
[23:20] Reserved
[19:18] Way
[17:16] BankSel
[15:14] Unused
[13:6] Index [13:6]
[5:0] Reserved

Table A6-16 L1 data TLB location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x0A
[23:6] Reserved
[5:0] TLB Entry (0->47)

Data cache reads return 64 bits of data in Data Register 0, Data Register 1, and Data Register 2. If cache protection is supported, Data Register 2 is used to report ECC information using the format shown in the following tables.

The following table shows the data that is returned from accessing the L1 data cache tag RAM with ECC.

Table A6-17 L1 data cache tag format with ECC

Register Bit field Description
Data Register 0 [63:41] 0
[40:34] ECC
[33] Non-secure identifier for the physical address
[32:5] Physical address [39:12]
[4:3] Reserved
[2] Transient/WBNA
[1:0]

MESI

00Invalid
01Shared
10Exclusive
11Modified with respect to the L2 cache
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0

The following table shows the data that is returned from accessing the L1 data cache tag RAM without ECC.

Table A6-18 L1 data cache tag format without ECC

Register Bit field Description
Data Register 0 [63:34] 0
[33] Non-secure identifier for the physical address
[32:5] Physical address [39:12]
[4:3] Reserved
[2] Transient/WBNA
[1:0]

MESI

00Invalid
01Shared
10Exclusive
11Modified
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0

The following table shows the data that is returned from accessing the L1 data cache data RAM with ECC.

Table A6-19 L1 data cache data format with ECC

Register Bit field Description
Data Register 0 [63:0] Word1_data [31:0], Word0_data [31:0]
Data Register 1 [63:0] Word3_data [31:0], Word2_data [31:0]
Data Register 2 [63:32] 0
[31:0] Word3_poison, Word3_ecc [6:0], Word2_poison, Word2_ecc [6:0], Word1_poison, Word1_ecc [6:0], Word0_poison, Word0_ecc [6:0]

The following table shows the data that is returned from accessing the L1 data cache data RAM without ECC.

Table A6-20 L1 data cache data format without ECC

Register Bit field Description
Data Register 0 [63:0] Word1_data [31:0], Word0_data [31:0]
Data Register 1 [63:0] Word3_data [31:0], Word2_data [31:0]
Data Register 2 [63:0] 0

The following table shows the data that is returned from accessing the L1 data TLB RAM.

Table A6-21 L1 data TLB cache format

Register Bit field Description
Data Register 0 [63:62]

Virtual address [13:12]

[58] Outer-shared
[57] Inner-shared
[52:50]

Memory attributes:

000Device nGnRnE
001Device nGnRE
010Device nGRE
011Device GRE
100Non-cacheable
101Write-Back No-Allocate
110Write-Back Transient
111Write-Back Read-Allocate and Write-Allocate
[38:36]

Page size:

0004KB
00116KB
01064KB
011256KB
100Reserved
1012MB
110512MB
111Reserved
[35] Non-secure
[34:33]

Translation regime:

00Secure EL1/EL0
01Secure EL3
10Non-secure EL1/EL0
11Non-secure EL2
[32:17] ASID
[16:1] VMID
[0] Valid
Data Register 1 [62:35]

Physical address [39:12]

[34:0] Virtual address[48:14]
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