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Arm Cortex‑A76 Core Technical Reference Manual : L1 data memory system

L1 data memory system

The L1 data cache is organized as a Virtually Indexed, Physically Tagged (VIPT) cache featuring four ways.

Data cache invalidate on reset

The Armv8-A architecture does not support an operation to invalidate the entire data cache. If software requires this function, it must be constructed by iterating over the cache geometry and executing a series of individual invalidate by set/way instructions.

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