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Arm Cortex‑A76 Core Technical Reference Manual : Specific behaviors on aborts and memory attributes

Specific behaviors on aborts and memory attributes

This section describes specific behaviors caused by aborts and also describes memory attributes.

MMU responses

When one of the following translation is completed, the MMU generates a response to the requester:

  • A L1 TLB hit.
  • A L2 TLB hit.
  • A translation table walk.

The response from the MMU contains the following information:

  • The PA corresponding to the translation.
  • A set of permissions.
  • Secure or Non-secure.
  • All the information required to report aborts. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more details.
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