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Arm Cortex‑A76 Core Technical Reference Manual : Data L1 TLB

Data L1 TLB

The data L1 TLB is a 48-entry fully associative TLB that is used by load and store operations. The cache entries have 4KB, 16KB, 64KB, 2MB, and 512MB granularity of VA to PA mappings only.

A hit in the data L1 TLB provides a single CLK cycle access to the translation, and returns the PA to the data cache for comparison. It also checks the access permissions to signal a Data Abort.

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