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Arm Cortex‑A76 Core Technical Reference Manual : Instruction L1 TLB

Instruction L1 TLB

The instruction L1 TLB is implemented as a 48-entry fully associative structure. This TLB caches entries at the 4KB, 16KB, 64KB, 2MB, and 32MB granularity of VA to PA mapping only.

A hit in the instruction L1 TLB provides a single CLK cycle access to the translation, and returns the PA to the instruction cache for comparison. It also checks the access permissions to signal an Instruction Abort.

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