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Arm Cortex‑A76 Core Technical Reference Manual Revision r3p0
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Arm Cortex‑A76 Core Technical Reference Manual : L2 TLB
The L2 TLB structure is shared by instruction and data. It handles misses from the instruction and data L1 TLBs.
The following table describes the characteristic that applies to the L2
A5-3 Characteristic of the L2 TLB
5-way, set associative, 1280-entry cache
VA to PA mappings for 4KB, 16KB, 64KB, 2MB, 32MB, 512MB, and
1GB block sizes.
Intermediate physical address
(IPA) to PA mappings for 2MB and 1GB (in a 4KB translation granule), 32MB (in a
16K translation granule), and 512MB (in a 64K granule) block sizes. Only
Non-secure EL1 and EL0 stage 2 translations are cached.
Intermediate PAs obtained during a translation table walk.
Access to the L2 TLB usually takes three cycles. If a different page or
block size mapping is used, then access to the L2 TLB can take longer.
The L2 TLB supports four translation table walks in parallel (four TLB misses),
and can service two TLB lookups while the translation table walks are in progress. If there
are six successive misses, the L2 TLB will stall.
The main TLB is invalidated automatically at reset unless the
DISCACHEINVLD signal is set HIGH when the Cortex®‑A76 core is reset. This signal must only be used in diagnostic mode. If
caches are not invalidated on reset, their functionality cannot be guaranteed. See the
Shared Unit Technical Reference Manual for more information on