The Cortex®‑A76 core contains a core power domain (PDCPU), and a core top-level SYS power domain (PDSYS) where all the Cortex‑A76 core I/O signals go through.
The PDCPU power domain contains all
enyo_cpu logic and part of the core asynchronous bridge that belongs to the VCPU domain. The Advanced SIMD and floating-point unit are included in the PDCPU power domain and is not supported as a separate power domain. The L1 and L2 RAMs are included in the PDCPU power domain and are not part of a separate power domain.
The PDSYS power domain contains the part of the core asynchronous bridge that belongs to the DSU power domain.
NoteThere are additional system power domains in the DSU. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for information.
The following table shows the power domain that the Cortex‑A76 core supports.
Table A4-1 Power domain description
The domain includes the Advanced SIMD and floating-point block, the L1 and L2 TLBs, L1 and L2 cache RAMs, and Debug registers that are associated with the Cortex‑A76 core.
<n> is the number of Cortex‑A76 cores. The number represents core 0, core 1, core 2, and core 3. If a core is not present, the corresponding power domain is not present.
|PDSYS||Top-level hierarchy and everything outside u_vcpu||
The domain is the interface between Cortex‑A76 and the DSU. It contains the cluster clock domain logic of the CPU bridge. The CPU Bridge contains all asynchronous bridges for crossing clock domains, and is split with one half of each bridge in the core clock domain and the other half in the relevant cluster domain. All core I/O signals go through the CPU bridge and the SYS power domain.
The domain is shared between the and hierarchies, and contains:
Clamping cells between power domains are inferred through power intent files rather than instantiated in the RTL.
The following figure shows an example of the organization of the power domains.
Figure A4-2 Cortex‑A76 core power domain diagram at enyo_core level
The following figure shows the power domains in the DSU, where everything in the same color is part of the same power domain. The example shows four Cortex‑A76 cores. The number of Cortex‑A76 cores can vary, and the number of domains increases based on the number of Cortex‑A76 cores present.
This example only shows the power domains that are associated with the Cortex‑A76 cores, other power domains are required for a DSU.
Figure A4-3 Cortex‑A76 power domains at enyo_core level