You copied the Doc URL to your clipboard.

Arm Cortex‑A76 Core Technical Reference Manual : Instruction fetch

Instruction fetch

The instruction fetch unit fetches instructions from the L1 instruction cache and delivers the instruction stream to the instruction decode unit.

The instruction fetch unit includes:

  • A 64KB, 4-way, set associative L1 instruction cache with 64-byte cache lines and optional parity protection.
  • A fully associative L1 instruction TLB with native support for 4KB, 16KB, 64KB, 2MB, and 32MB page sizes.
  • A dynamic branch predictor.
Was this page helpful? Yes No