L1 data memory system
The L1 data memory system executes load and store instructions and encompasses the L1 data side memory system. It also services memory coherency requests.
The load/store unit includes:
- A 64KB, 4-way, set associative L1 data cache with 64-byte cache lines and optional ECC protection per 32 bits.
- A fully associative L1 data TLB with native support for 4KB, 16KB, 64KB, 2MB, and 512MB page sizes.