AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
AFSR1_EL2 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL2. This register is not used in the Cortex®‑A76 core.
Bit field descriptions
AFSR1_EL2 is a 32-bit register, and is part of:
- The Virtualization registers functional group.
- The Exception and fault handling registers functional group.
- The IMPLEMENTATION DEFINED functional group.
Figure B2-8 AFSR1_EL2 bit assignments
- RES0, [31:0]
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.