CLIDR_EL1, Cache Level ID Register, EL1
The CLIDR_EL1 identifies the type of cache, or caches, implemented at each level, up to a maximum of seven levels.
It also identifies the Level of Coherency (LoC) and Level of Unification (LoU) for the cache hierarchy.
Bit field descriptions
CLIDR_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-15 CLIDR_EL1 bit assignments
- RES0, [63:33]
- ICB, [32:30]
Inner cache boundary. This field indicates the boundary between the inner and the outer domain:
L2 cache is the highest inner level.
L3 cache is the highest inner level.
- LoUU, [29:27]
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
No levels of cache need to cleaned or invalidated when cleaning or invalidating to the Point of Unification. This is the value if no caches are configured.
- LoC, [26:24]
Indicates the Level of Coherency for the cache hierarchy:
L3 cache is not implemented.
L3 cache is implemented.
- LoUIS, [23:21]
Indicates the Level of Unification Inner Shareable (LoUIS) for the cache hierarchy.
No cache level needs cleaning to Point of Unification.
- RES0, [20:9]
No cache at levels L7 down to L4.
- Ctype3, [8:6]
Indicates the type of cache if the core implements L3 cache. If present, unified instruction and data caches at Level 3:
Both per-core L2 and cluster L3 caches are present.
All other options.
If Ctype2 has a value of
0b000, then the value of Ctype3 must be ignored.
- Ctype2, [5:3]
Indicates the type of unified instruction and data caches at Level 2:
Either per-core L2 or cluster L2 cache is present.
All other options.
- Ctype1, [2:0]
Indicates the type of cache implemented at L1:
Separate instruction and data caches at L1.
- There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.