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Arm Cortex‑A76 Core Technical Reference Manual : CPACR_EL1, Architectural Feature Access Control Register, EL1

CPACR_EL1, Architectural Feature Access Control Register, EL1

The CPACR_EL1 controls access to trace functionality and access to registers associated with Advanced SIMD and floating-point execution.

Bit field descriptions

CPACR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.

Figure B2-16 CPACR_EL1 bit assignments


RES0, [31:29]
RES0 Reserved.
TTA, [28]

Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1, from both Execution states. This bit is RES0. The core does not provide System Register access to ETM control.

Configurations

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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