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Arm Cortex‑A76 Core Technical Reference Manual : CPTR_EL2, Architectural Feature Trap Register, EL2

CPTR_EL2, Architectural Feature Trap Register, EL2

The CPTR_EL2 controls trapping to EL2 for accesses to CPACR, trace functionality and registers associated with Advanced SIMD and floating-point execution. It also controls EL2 access to this functionality.

Bit field descriptions

CPTR_EL2 is a 32-bit register, and is part of the Virtualization registers functional group.

Figure B2-17 CPTR_EL2 bit assignments


TTA, [20]

Trap Trace Access.

This bit is not implemented. RES0.

Configurations

RW fields in this register reset to UNKNOWN values.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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