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Arm Cortex‑A76 Core Technical Reference Manual : CPUACTLR_EL1, CPU Auxiliary Control Register, EL1

CPUACTLR_EL1, CPU Auxiliary Control Register, EL1

The CPUACTLR_EL1 provides IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUACTLR_EL1 is a 64-bit register, and is part of the IMPLEMENTATION DEFINED registers functional group.

Figure B2-19 CPUACTLR_EL1 bit assignments


Reserved, [63:0]
Reserved for Arm® internal use.
Configurations

CPUACTLR_EL1 is common to the Secure and Non-secure states.

Usage constraints

Accessing the CPUACTLR_EL1

The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled.

Setting many of these bits can cause significantly lower performance on your code. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.

This register is accessible as follows:

This register can be read with the MRS instruction using the following syntax:

MRS <Xt>,<systemreg>

This register can be written with the MSR instruction using the following syntax:

MSR <systemreg>, <Xt>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C1_0 11 000 1111 0001 000
Accessibility

This register is accessible in software as follows:

<systemreg> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
S3_0_C15_C1_0 x x 0 - RW n/a RW
S3_0_C15_C1_0 x 0 1 - RW RW RW
S3_0_C15_C1_0 x 1 1 - n/a RW RW

'n/a' Not accessible. The core cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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