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Arm Cortex‑A76 Core Technical Reference Manual : CSSELR_EL1, Cache Size Selection Register, EL1

CSSELR_EL1, Cache Size Selection Register, EL1

CSSELR_EL1 selects the current Cache Size ID Register (CCSIDR_EL1), by specifying:

  • The required cache level.
  • The cache type, either instruction or data cache.

For details of the CCSIDR_EL1, see CCSIDR_EL1, Cache Size ID Register, EL1.

Bit field descriptions

CSSELR_EL1 is a 32-bit register, and is part of the Identification registers functional group.

Figure B2-28 CSSELR_EL1 bit assignments


[31:4]
res0 Reserved.
Level, [3:1]

Cache level of required cache:

000 L1.
001 L2.
010L3, if present.

The combination of Level=001 and InD=1 is reserved.

The combinations of Level and InD for 0100 to 1111 are reserved.

InD, [0]

Instruction not Data bit:

0 Data or unified cache.
1 Instruction cache.

The combination of Level=001 and InD=1 is reserved.

The combinations of Level and InD for 0100 to 1111 are reserved.

Configurations

If a cache level is missing but CSSELR_EL1 selects this level, then a CCSIDR_EL1 read returns an UNKNOWN value.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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