CTR_EL0, Cache Type Register, EL0
The CTR_EL0 provides information about the architecture of the caches.
Bit field descriptions
CTR_EL0 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-29 CTR_EL0 bit assignments
- RES1, 
- RES0, [30:29]
- IDC, 
Data cache clean requirements for instruction to data coherence:
Data cache clean to the point of unification is required for instruction to data coherence, unless CLIDR_EL1.LoC == 0b000 or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000). .
Data cache clean to the point of unification is not required for instruction to data coherence.
IDC reflects the inverse value of the BROADCASTCACHEMAINTPOU pin.
- CWG, [27:24]
Cache write-back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
Cache write-back granule size is 16 words.
- ERG, [23:20]
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
Exclusive reservation granule size is 16 words.
- DminLine, [19:16]
Log2 of the number of words in the smallest cache line of all the data and unified caches that the core controls:
Smallest data cache line size is 16 words.
- L1Ip, [15:14]
Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
Physically Indexed Physically Tagged (PIPT).
- RES0, [13:4]
- IminLine, [3:0]
Log2 of the number of words in the smallest cache line of all the instruction caches that the core controls.
Smallest instruction cache line size is 16 words.
- There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.