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Arm Cortex‑A76 Core Technical Reference Manual : ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1

ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1

Register ERXMISC0_EL1 accesses the ERR<n>MISC0 register for the error record selected by ERRSELR_EL1.SEL.

If ERRSELR_EL1.SEL==0, then ERXMISC0_EL1 accesses the ERR0MISC0 register of the core error record. See ERR0MISC0, Error Record Miscellaneous Register 0.

If ERRSELR_EL1.SEL==1, then ERXMISC0_EL1 accesses the ERR1MISC0 register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

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