ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
The ID_AA64ISAR1_EL1 provides information about the instructions implemented in AArch64 state.
Bit field descriptions
ID_AA64ISAR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-41 ID_AA64ISAR1_EL1 bit assignments
- RES0, [63:24]
- LRCPC, [23:20]
Indicates whether load-acquire (
LDA) instructions are implemented for a Release Consistent core consistent RCPC model.
LDAPRinstructions are implemented in AArch64.
- RES0, [19:4]
- DC CVAP, [3:0]
Indicates whether Data Cache, Clean to the Point of Persistence (
DC CVAP) instructions are implemented.
DC CVAPis supported in AArch64.
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.