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Arm Cortex‑A76 Core Technical Reference Manual : ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1

ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1

The ID_DFR0_EL1 provides top-level information about the debug system in AArch32.

Bit field descriptions

ID_DFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-48 ID_DFR0_EL1 bit assignments


RES0, [31:28]
RES0 Reserved.
PerfMon, [27:24]

Indicates support for performance monitor model:

4 Support for Performance Monitor Unit version 3 (PMUv3) system registers, with a 16-bit evtCount field.
MProfDbg, [23:20]

Indicates support for memory-mapped debug model for M profile cores:

0 This product does not support M profile Debug architecture.
MMapTrc, [19:16]

Indicates support for memory-mapped trace model:

1 Support for Arm trace architecture, with memory-mapped access.

In the Trace registers, the ETMIDR gives more information about the implementation.

CopTrc, [15:12]

Indicates support for coprocessor-based trace model:

0 This product does not support Arm trace architecture.
RES0, [11:8]
RES0 Reserved.
CopSDbg, [7:4]

Indicates support for coprocessor-based Secure debug model:

8 This product supports the Armv8.2 Debug architecture.
CopDbg, [3:0]

Indicates support for coprocessor-based debug model:

8 This product supports the Armv8.2 Debug architecture.
Configurations
There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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