ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
The ID_ISAR2_EL1 provides information about the instruction sets implemented by the core in AArch32.
Bit field descriptions
ID_ISAR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-51 ID_ISAR2_EL1 bit assignments
- Reversal, [31:28]
Indicates the implemented Reversal instructions:
- PSR_AR, [27:24]
Indicates the implemented A and R profile instructions to manipulate the PSR:
MSRinstructions, and the exception return forms of data-processing instructions.
The exception return forms of the data-processing instructions are:
- In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set.
- In the T32 instruction set, the
- MultU, [23:20]
Indicates the implemented advanced unsigned Multiply instructions:
- MultS, [19:16]
Indicates the implemented advanced signed Multiply instructions.
SMULWTinstructions, and the Q bit in the PSRs.
- Mult, [15:12]
Indicates the implemented additional Multiply instructions:
- MultiAccessInt, [11:8]
Indicates the support for interruptible multi-access instructions:
No support. This means the LDM and STM instructions are not interruptible.
- MemHint, [7:4]
Indicates the implemented memory hint instructions:
- LoadStore, [3:0]
Indicates the implemented additional load/store instructions:
The Load Acquire (
LDAEXD) and Store Release (
In an AArch64-only implementation, this register is UNKNOWN.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, and ID_ISAR6_EL1. See:
- ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1.
- ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1.
- ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1.
- ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1.
- ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1.
- ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.