ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
The ID_ISAR4_EL1 provides information about the instruction sets implemented by the core in AArch32.
Bit field descriptions
ID_ISAR4_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-53 ID_ISAR4_EL1 bit assignments
- SWP_frac, [31:28]
Indicates support for the memory system locking the bus for
SWPBinstructions not implemented.
- PSR_M, [27:24]
Indicates the implemented M profile instructions to modify the PSRs:
- SynchPrim_frac, [23:20]
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions:
- Barrier, [19:16]
Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
- SMC, [15:12]
Indicates the implemented
- WriteBack, [11:8]
Indicates the support for Write-Back addressing modes:
Core supports all the Write-Back addressing modes as defined in Arm®v8‑A.
- WithShifts, [7:4]
Indicates the support for instructions with shifts.
- Support for shifts of loads and stores over the range LSL 0-3.
- Support for other constant shift options, both on load/store and other instructions.
- Support for register-controlled shift options.
- Unpriv, [3:0]
Indicates the implemented unprivileged instructions.
In an AArch64-only implementation, this register is UNKNOWN.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR5_EL1, and ID_ISAR6_EL1. See:
- ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1.
- ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1.
- ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1.
- ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1.
- ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1.
- ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.