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Arm Cortex‑A76 Core Technical Reference Manual : ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

The ID_ISAR5_EL1 provides information about the instruction sets that the core implements.

Bit field descriptions

ID_ISAR5_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-54 ID_ISAR5_EL1 bit assignments


[31:28]
RES0 Reserved.
RDM, [27:24]

VQRDMLAH and VQRDMLSH instructions in AArch32. The value is:

0x1 VQRDMLAH and VQRDMLSH instructions are implemented.
[23:20]
RES0 Reserved.
CRC32, [19:16]

Indicates whether CRC32 instructions are implemented in AArch32 state. The value is:

0x1 CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions are implemented.
SHA2, [15:12]

Indicates whether SHA2 instructions are implemented in AArch32 state. The possible values are:

0x0 No SHA2 instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x1 SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented. This is the value when the Cryptographic Extensions are implemented and enabled.
SHA1, [11:8]

Indicates whether SHA1 instructions are implemented in AArch32 state. The possible values are:

0x0 No SHA1 instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x1 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented. This is the value when the Cryptographic Extensions are implemented and enabled.
AES, [7:4]

Indicates whether AES instructions are implemented in AArch32 state. The possible values are:

0x0 No AES instructions implemented. This is the value when the Cryptographic Extensions are not implemented or are disabled.
0x2
  • AESE, AESD, AESMC, and AESIMC implemented.
  • PMULL and PMULL2 instructions operating on 64-bit data.

This is the value when the Cryptographic Extensions are implemented and enabled.

SEVL, [3:0]

Indicates whether the SEVL instruction is implemented:

0x1 SEVL implemented to send event local.
Configurations

ID_ISAR5 must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR6_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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