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Arm Cortex‑A76 Core Technical Reference Manual : ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1

ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1

The ID_MMFR2_EL1 provides information about the implemented memory model and memory management support in AArch32.

Bit field descriptions

ID_MMFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-58 ID_MMFR2_EL1 bit assignments


HWAccFlg, [31:28]

Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7 implementation:

0x0 Not supported.
WFIStall, [27:24]

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:

0x1 Support for WFI stalling.
MemBarr, [23:20]

Memory Barrier. Indicates the supported CP15 memory barrier operations.

0x2

Supported CP15 memory barrier operations are:

  • Data Synchronization Barrier (DSB).
  • Instruction Synchronization Barrier (ISB).
  • Data Memory Barrier (DMB).
UniTLB, [19:16]

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.

0x6

Supported unified TLB maintenance operations are:

  • Invalidate all entries in the TLB.
  • Invalidate TLB entry by MVA.
  • Invalidate TLB entries by ASID match.
  • Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a shared unified TLB operation.
  • Invalidate Hyp mode unified TLB entry by MVA.
  • Invalidate entire Non-secure EL1 and EL0 unified TLB.
  • Invalidate entire Hyp mode unified TLB.
  • TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.
  • TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.
HvdTLB, [15:12]

Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:

0x0

Not supported.

LL1HvdRng, [11:8]

L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a Harvard cache implementation:

0x0 Not supported.
L1HvdBG, [7:4]

L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch operations, for a Harvard cache implementation:

0x0 Not supported.
L1HvdFG, [3:0]

L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch operations, for a Harvard cache implementation:

0x0 Not supported.
Configurations

Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1. See:

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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