ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
The ID_PFR0_EL1 provides top-level information about the instruction sets supported by the core in AArch32.
Bit field descriptions
ID_PFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-61 ID_PFR0_EL1 bit assignments
- RAS, [31:28]
RAS extension version. The value is:
Version 1 of the RAS extension is present.
- RES0, [27:20]
- CSV2, [19:16]
This device does not disclose whether branch targets trained in one context can affect speculative execution in a different context.
Branch targets trained in one context cannot affect speculative execution in a different hardware described context. This is the reset value.
- State3, [15:12]
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
Core does not support the T32EE instruction set.
- State2, [11:8]
Indicates support for Jazelle. This value is:
Core supports trivial implementation of Jazelle.
- State1, [7:4]
Indicates support for T32 instruction set. This value is:
Core supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions.
- State0, [3:0]
Indicates support for A32 instruction set. This value is:
A32 instruction set implemented.
- There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.