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Arm Cortex‑A76 Core Technical Reference Manual : ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1

ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1

The ID_PFR1_EL1 provides information about the programmers model and architecture extensions supported by the core.

Bit field descriptions

ID_PFR1_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-62 ID_PFR1_EL1 bit assignments


GIC CPU, [31:28]

GIC CPU support:

0 GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
1 GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
Virt_frac, [27:24]
0

No features from the Armv7 Virtualization Extensions are implemented.

Sec_frac, [23:20]
0

No features from the Armv7 Virtualization Extensions are implemented.

GenTimer, [19:16]

Generic Timer support:

1 Generic Timer supported.
Virtualization, [15:12]

Virtualization support:

0 Virtualization not implemented.
MProgMod, [11:8]

M profile programmers model support:

0 Not supported.
Security, [7:4]

Security support:

0 Security not implemented.
ProgMod, [3:0]

Indicates support for the standard programmers model for Armv4 and later.

Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:

0 Not supported.
Configurations

There are no configuration notes.

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