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Arm Cortex‑A76 Core Technical Reference Manual : SCTLR_EL1, System Control Register, EL1

SCTLR_EL1, System Control Register, EL1

The SCTLR_EL1 provides top-level control of the system, including its memory system, at EL1 and EL0.

Bit field descriptions

SCTLR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.

This register resets to 0x30D50838.

Figure B2-74 SCTLR_EL1 bit assignments


RES0, [31:30]
RES0

Reserved.

RES1, [29:28]
RES1

Reserved.

RES0, [27]
RES0

Reserved.

EE, [25]

Exception endianness. The value of this bit controls the endianness for explicit data accesses at EL1. This value also indicates the endianness of the translation table data for translation table lookups. The possible values of this bit are:

0 Little-endian.
1 Big-endian.
ITD, [7]

This field is RAZ/WI.

RES0, [6]
RES0

Reserved.

CP15BEN, [5]

CP15 barrier enable. The possible values are:

0 CP15 barrier operations disabled. Their encodings are UNDEFINED.
1 CP15 barrier operations enabled.
M, [0]

MMU enable. The possible values are:

0 EL1 and EL0 stage 1 MMU disabled.
1 EL1 and EL0 stage 1 MMU enabled.
Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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