TCR_EL3, Translation Control Register, EL3
The TCR_EL3 controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.
Bit field descriptions
TCR_EL3 is a 32-bit register and is part of the Virtual memory control registers functional group.
Figure B2-79 TCR_EL3 bit assignments
Bits[28:21], architecturally defined, are implemented in the core.
- HD, 
Dirty bit update. The possible values are:
Dirty bit update is disabled.
Dirty bit update is enabled.
- HA, 
Stage 1 Access flag update. The possible values are:
Stage 1 Access flag update is enabled.
Stage 1 Access flag update is disabled.
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.