TTBR0_EL2, Translation Table Base Register 0, EL2
The TTBR0_EL2 holds the base address of the translation table for the stage 1 translation of memory accesses from EL2.
Bit field descriptions
TTBR0_EL2 is a 64-bit register, and is part of the Virtual memory control registers functional group.
Figure B2-81 TTBR0_EL2 bit assignments
- RES0, [63:48]
- BADDR, [47:1]
Translation table base address, bits[47:x]. Bits [x-1:1] are RES0.
x is based on the value of TCR_EL2.T0SZ, the stage of translation, and the memory translation granule size.
For instructions on how to calculate it, see the Arm® Architecture Reference Manual Arm®v8, for Arm®v8-A architecture profile.
The value of x determines the required alignment of the translation table, that must be aligned to 2x bytes.
If bits [x-1:1] are not all zero, this is a misaligned translation table base address. Its effects are CONSTRAINED UNPREDICTABLE, where bits [x-1:1] are treated as if all the bits are zero. The value read back from those bits is the value written.
- CnP, 
Common not Private. The possible values are:
CnP is not supported.
CnP is supported.
When the Virtualization Host Extension is activated, TTBR0_EL2 has the same bit assignments as TTBR0_EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.